1. Field of the Invention
The present invention relates to a multiport memory having a random access port and a serial access port, in which data is transmitted from the random access port to the serial access port.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing part of a general multiport memory in which data is transmitted from a random access port (RAM port) to a serial access port (SAM port). In FIG. 1, BL and BL denote a pair of bit lines and WL denotes a word line.
Memory cells, e.g., dynamic memory cells MC are provided at the intersections of the pair of bit lines BL and BL and word lines WL.
Each of the memory cells MC has a selection MOS transistor 21 and a capacitor 22. The gate of each MOS transistor 21 is connected to each word line WL and the source thereof is connected to the bit line BL or BL. The capacitor 22 is connected between the drain of the MOS transistor 21 and a reference potential, e.g., a ground potential V.sub.SS.
A sense amplifier 23 is inserted in a middle portion of the pair of bit lines BL and BL. The sense amplifier 23 amplifies a minute difference between the potentials output to the bit lines BL and BL when data is read from the memory cell MC. The sense amplifier 23 is activated on the basis of a control signal SEN.
Column selection gate MOS transistors 24 and 25 are connected between the pair of bit lines BL and BL and a pair of data lines DQ and DQ for the RAM port. The gates of the transistors 24 and 25 are connected to a column selection line CSL.
Load elements 26 and 27, each consisting of a MOS transistor serving as a load transistor, are inserted between a source potential V.sub.CC and the pair of data lines DQ and DQ. The load elements 26 and 27 are always conductive.
A data register 30 for the SAM port is connected to the pair of bit lines BL and BL through data transmission gate MOS transistors 28 and 29. The data register 30 is constituted by, for example, a flip-flop having two inverters 31 and 32. The gates of the data transmission gate MOS transistors 28 and 29 are connected to a data transmission control line TRG.
In the multiport memory as described above, when data read from a memory cell MC of the RAM port is transmitted to the SAM port, the column selection line CSL and a DQ sense amplifier (not shown) for amplifying data on the data lines DQ and DQ are inhibited from being activated, until data amplified by the sense amplifier 23 is determined, as in a normal RAM.
A conventional data reading operation of the multiport memory will be described with reference to the timing charts shown in FIGS. 2 ((A) to (G)).
A word line WL is selected in response to an address input (normally, a row address signal). A potential is read from the memory cell MC connected to the word line WL to one of the bit lines BL and BL. As a result, the potential difference between the bit lines BL and BL begins to increase (FIG. 2 (A)).
Then, a signal SEN is lowered to a "L" level at a timing and the sense amplifier 23 is activated (FIG. 2 (C)).
As a result of the activation of the sense amplifier 23, the potential difference between the bit lines BL and BL is increased to be a difference between the source potential V.sub.CC and the ground potential V.sub.SS. When the potential difference between the lines BL and BL becomes sufficiently great, the column selection line CSL is activated and the column selection MOS transistors 24 and 25 are turned on (FIG. 2 (D)).
Thereafter, data is transmitted from the bit lines BL and BL to the data lines DQ and DQ through the MOS transistors 24 and 25. When a predetermined period of time elapses, the data transmission control line TRG is activated and the data transmission gate MOS transistors 28 and 29 are turned on (FIG. 2 (E)).
As a result, data is transmitted from the bit lines BL and BL to the data register 30 for the SAM port.
When the data transmission gate MOS transistor 28 and 29 are in the ON state and the data is being transmitted to the data register 30 for the SAM port, the column selection MOS transistors 24 and 25 are also in the ON state.
The data lines DQ and DQ are connected to the load elements 26 and 27 constituted by the load transistors, as described above. Therefore, when the column selection line CSL is activated and the bit lines BL and BL are electrically connected to the data lines DL and DL, one of the bit lines BL and BL, which is set to the "L" level, is charged by the source potential V.sub.CC through the data lines DQ and DQ.
The potential of the bit line of the "L" level increases by a potential .DELTA.V from the ground potential V.sub.SS, as shown in FIG. 2 (A), due to the existence of the load transistors. In this state, when the data transmission control line TRG is activated and data is transmitted from the bit lines BL and BL to the data resistor 30 for the SAM port, the high potential level of the data resistor 30 cannot be discharged since the bit line potential of the "L" level has been increased by .DELTA.V.
In a normal condition, the memory state of the data resister 30 can be inverted by using the data on the bit lines BL and BL, as shown in FIG. 2 (F). However, in some cases, it cannot be converted, as shown in FIG. 2 (G), in which case, data cannot be transmitted normally. As a result, memory cell data may be damaged.
As described above, the conventional multiport memory has the drawback that an abnormal transmission may occur when data is transmitted from the RAM port to the SAM port, resulting in damage of the memory cell data of the RAM port.